1. Field of the Invention
The present invention relates generally to interfacing computer memory devices and particularly to computer memory interfaces. More particularly, the present invention relates to a system that automatically adjusts the timing of memory interface signals.
2. Background of the Invention
Computer systems, which can be generally defined as electronic devices which retrieve, process, and store data, require a certain amount of computer memory in which to store computer programs, data, and variables used during processing. Computer memory is more commonly known as random access memory (RAM), since the computer may access any portion of the memory at any time. Most RAM devices in use today are manufactured to be volatile, meaning that the memory contents are valid only when the RAM devices are supplied with electric power. Some computer devices use nonvolatile RAM as well, devices which hold memory contents even when the power supply is cut off. Devices that use random access memory typically include a memory controller that couples to the RAM. The memory controller receives memory requests from the computer system and transmits the proper sequence of signals to the RAM to perform the memory transactions. The computer system is often called a "host system," since it includes the memory controller that interfaces the memory device.
Currently, there are many types of RAM architectures, two common types of volatile RAM being dynamic RAM (DRAM) and static RAM (SRAM). Each storage element (or "bit") of SRAM is constructed using a flip-flop, a basic storage device constructed typically requiring approximately six transistors. In contrast, DRAM requires only one transistor per bit and is therefore generally cheaper and more compact than SRAM. SRAM is typically faster than DRAM and much simpler to use, however. Consequently, SRAM is typically used in computer devices that require fast but small memories, while DRAM is typically used when a large amount of RAM is needed. In fact, many microprocessor-based systems use a combination of DRAM and SRAM, constructing the large main memory from DRAM chips and using SRAM for the smaller memory devices, such as memory caches for the processor. A number of DRAM architectures are available, including synchronous DRAM (SDRAM), extended data output DRAM (EDO DRAM), and Rambus.TM. DRAM (RDRAM).
Conventional DRAM chips receive a plurality of input signals which define parameters such as the location, or address, of the memory data and which transmit the memory data. A read or write transaction with a DRAM generally involves two steps. First, address and control signals are asserted to the DRAM, allowing the DRAM to prepare for the data transfer. Second, the DRAM reads or writes the data, completing the data transfer. Synchronous DRAM's operate similarly to conventional DRAM's, although SDRAM signals include a reference clock signal to which the other SDRAM signals are synchronized. SDRAM's also typically support pipelining, which allows the SDRAM accept address and control signals for a one memory transaction while transacting a previous memory request via the data signals. For a more detailed description of DRAM, SDRAM, and other memory devices, refer to The Art of Electronics by Horowitz and Hill, pages 812-820 (Cambridge University Press, 1989) or Computer Organization & Design by Hennessy and Patterson, pages B21-B35 (Morgan Kaufmann Publishers, 1994).
An important consideration for selecting a memory device in a computer system is the speed at which data can be written to and read from the memory device. Memory speed is also commonly known as "bandwidth," a term which refers to the frequency content of the memory signals. Generally, a higher speed memory device is more efficient, because it can supply data at a faster rate (or "higher bandwidth"). In fact, memory bandwidth is often considered a crucial factor in evaluating the performance of processor-based systems. The emergence of new memory technologies and improvements in existing memory architectures are helping to increase current memory bandwidths, thus improving computer performance.
Typical computer systems use SDRAM's that operate at frequencies of up to approximately 100 million cycles per second, or 100 megahertz (MHz). More recently, SDRAM's operating at 200 MHz have been developed. Despite the increased performance that the newer, faster devices provide, these devices can be challenging to use due to timing requirements. A signal that oscillates at 200 MHz has a cycle duration, known as the "period," of 5 billionths of a second, or 5 nanoseconds (ns). Digital signals typically oscillate repeatedly between two voltages: a low voltage and a high voltage. The period of the signal describes the length of time between adjacent rising edges of the signal, where the rising edge of the signal represents the transition from the low voltage to the high voltage. To ensure adequate performance, the SDRAM signals must be transmitted to within an accuracy of about one-half the period, or no more than 2.5 ns for a 200 MHz device. If memory timing requirements are not met, then the memory device may not function properly, and the memory read and write data may contain errors.
Achieving signal timing accuracy can be very difficult in practice. The natural laws of electromagnetics which govern the transmission of electronic signals tend to introduce various amounts of delay and distortion to high frequency signals. These "electromagnetic" effects are commonly known as capacitive (or inductive) loading, which causes signal delay, and ringing, which causes signal distortion. In addition to the signal bandwidth, the physical location and dimensions of the signal conductors (known as signal "traces") also affect the transmission behavior, as does the level of current used to transmit the signals.
Under capacitive loading, certain signals may travel across the circuit board at a delay with respect to the synchronizing clock signal. It is common to adjust for signal delays by inserting delay buffers, devices which delay electronic signals, into the SDRAM interface. Often, each signal transmitted or received by the memory controller will be delay-buffered. By setting the proper amount of delay for each buffer, the memory signals can be synchronized with the clock signal.
A significant problem with using delay buffers is that the optimum delay can be difficult to predict before the circuit board is manufactured. First, different memory technologies may include different signals or may operate at different speeds. To accommodate a wide variety of memory devices, the delay buffers must be specially configured for each new memory system design. Even if the same type of memory device is used in a different computer system, however, differences in signal traces on the circuit board can change the required delay settings considerably. In addition, it is often desirable for circuit designers to use a standard memory interface that supports a variety of standard SDRAM devices. Such a modular design is generally more flexible and economical than designing a custom memory interface. Because memory devices may vary slightly among manufacturers, however, different SDRAM devices may require unique delay settings and require costly experimentation to determine the best delay settings.
Another problem is that, due to the inherent limitations of present computer chip and circuit board technology, the capacitive loading can fluctuate slightly from board to board during manufacturing. Thus, even a carefully designed circuit board may not meet memory signal timing requirements due to manufacturing imperfections.
For the foregoing reasons, a device capable of automatically optimizing and adjusting the memory signal timing of an existing computer system would greatly improve the speed and reliability of memory performance. Despite the apparent advantages that such a system would provide, to date no device has been developed that provides these features.